1. Field of the Invention
The present invention relates to a field of impedance control for semiconductor devices, and more particularly, to an impedance control circuit and method in a semiconductor device, capable of reducing an impedance mismatch.
2. Discussion of the Related Art
A semiconductor device typically includes pins to transmit and send data to and from other devices, and a data output circuit which functions as a data output buffer and a driver circuit to provide internal data to external devices. As an example, the pins may be connected to a transmission line such as printed wiring provided on a mounting substrate, in a semiconductor device incorporated into an electrical appliance. The pins are required to charge or discharge a floating capacitance or load capacitance (parasitic capacitance) existing on the mounting substrate. Matching an output impedance to an impedance of a transmission line should achieve the optimum transmission of an output signal. Matching an input impedance to the impedance of a transmission line should achieve the reception of input signals without distortion. The former is known to those in the art as an output impedance(ZQ) control and the latter is known as a chip termination(ZT) control. Generally the output impedance control is performed for an output driver and the chip termination control is performed for an input terminator.
An increasing trend in the field of electrical appliances is to decrease a swing width of a signal interfaced between semiconductor devices, thereby substantially reducing a delay time which occurs during the transfer of the signal. However, when the swing width of the signal is reduced, an influence of external noise increases, and a reflection of the output signal caused by impedance mismatch degrades the signal. Impedance mismatch can be caused by a number of factors, including external noise, or variations in power source voltage, operating temperatures and fabricating processes, etc. When output impedance(ZQ) or chip termination(ZT) controls are not performed properly, impedance mismatch occurs and both transmitted and received signals may be distorted, causing a number of potential problems. As an example, when a semiconductor device receives a distorted output signal through a receiver, a setup/hold fail or a decision error from improper input level may occur
Thus, some semiconductor memory devices have employed a programmable impedance control scheme to perform input/output impedance matching with external semiconductor devices. U.S. Pat. No. 6,307,424, discloses a programmable impedance control (PIC) circuit to perform programmable impedance control.
When performing impedance control with a High Speed Transceiver Logic (HSTL) interface, one extra pin is used to produce an output impedance within dozens of ohms of a desired value. In a semiconductor memory device employing such a scheme, it is frequently difficult to obtain and adaptively correct a precise output impedance value, due to many conditions such as varying power source voltages, operating temperatures, and manufacturing processes. U.S. Pat. No. 6,456,124 discloses a variable impedance control method.
In high-speed data transmission, as data transmission rates increase, so do the requirements for an on-chip termination. In the on-chip termination, a source termination is performed in an output driver(Dout) side, and a parallel termination is performed in a receiver side. TA signal can be transferred in a full swing even though the swing level of the signal is reduced, and so an effect of a reflected signal is reduced and integrity of the signal is improved.
A termination circuit, or terminator, can be created by using a parallel-sum impedance of a composed transistor array, the transistor array being constructed of a plurality of pull-up and pull-down transistors. A median signal is produced by pull-up resistance and pull-down resistance of the terminator, but a receiver recognizes the signal by using a separate reference voltage. When a mismatch of pull-up and pull-down resistances occurs within the transistor array of the terminator, the median signal is changed, having an adverse effect on a setup/hold window of the receiver.
In a prior art, there is an impedance mismatch of a 1-bit resolution between pull up and down resistances which limits the reduction in impedance mismatch that can occur. The prior art will be described in reference to FIGS. 1-3 as follows.
FIG. 1 is a block diagram illustrating a conventional impedance control circuit in a semiconductor device. FIG. 2 illustrates circuit blocks of FIG. 1 in greater detail. FIG. 3 illustrates an example of impedance mismatch between pull up and down resistance shown in FIG. 2.
FIG. 1 illustrates a circuit with an impedance detector 200, an impedance controller 100 and a driver 300. The driver 300 may comprise an output driver or a terminator. As shown in the circuit of FIG. 2, the impedance detector 200 outputs a pull-up output value XZQ in response to a pull-up control code data P<n:0>, to a detection pad connected between an external determination resistor RQ and a pull-up transistor array P1-P4, and outputs a pull-down output value DZQ to a resistance divider terminal commonly connected between pull-up and pull-down transistor arrays P10, P20-P40, N10 and N20-N40 in response to the pull-up control code data P<n:0> and the pull-down control code data N<n:0>.
The driver 300 includes the same transistor arrays P11, P21-P41 and N11, N21-N41 as the pull-up and pull-down transistor arrays of the impedance detector 200, and is selectively turned on in response to substantially the same pull-up control code data p<n:0> and pull-down control code data n<n:0> as the above pull-up control code data P<n:0> and pull-down control code data N<n:0>.
The impedance controller 100 performs a comparison on the pull-up and pull-down output values, the comparison used to adjust a counter which outputs the pull-up and pull-down control code data so that the pull-up output value and pull-down output value of the impedance detector 200 is adjusted to a value approximate to a predetermined reference value, e.g., half a power source voltage, and generates the pull-up control code data P<n:0> and the pull-down control code data N<n:0>. The impedance controller 100, functioning as a ZQ/ZT controller, properly controls the pull-up control code data P<n:0> and the pull-down control code data N<n:0>. Transistors within the pull-up and the pull-down transistor arrays are enabled or disabled based on the control code data, thereby adjusting a resistance value of the impedance detector 200 to closely approximate a resistance RQ within a range of resolution. The pull-up control code data p<n:0> and the pull-down control code data n<n:0> input to the driver 300, have the same value as data applied to the impedance detector 200, and the corresponding resistance value of the output driver 300 has the same resistance value as a resistance value of the impedance detector 100.
P-type MOS transistors P1-P4 within the pull-up transistor array shown in the upper side of FIG. 2 are selectively turned on or off by the pull-up control code data P<n:0>, and a parallel synthesis resistance value obtained through the turned-on transistors becomes approximated to the external determination resistance(RQ) value. The control by the pull-up control code data P<n:0> employs a digital control scheme causing quantization error. In generating the pull-up control code data, the impedance controller 100 selects a code to provide a resistance value less than the reference resistance value, as the pull-up control code data P<n:0>, so that the parallel synthesis resistance value becomes approximated to the predetermined reference resistance value or a target resistance value. The pull-up control code data P<n:0> is copied intact as a control code data P<n:0> for controlling pull-up transistors P10-P40 of the pull-up transistor array connected to a pull-down output terminal DZQ. The impedance controller 100 outputs a control code data N<n:0> and controls a pull-down resistance, on the basis of the pull-up resistance value provided by the pull-up control code data P<n:0>, so that transistors N10-N40 within an N-type transistor array positioned under the output terminal DZQ are turned on or off. Consequently, this is to provide a reference voltage to the output terminal DZQ. In generating the pull-down control code data, a code representing a resistance value greater than the reference resistance value is selected by the impedance controller 100.
In the circuit of FIG. 2, an impedance mismatch between pull-up and pull-down resistances may have a value corresponding to a maximum 1-bit resolution as shown in FIG. 3. FIG. 3 illustrates a maximum range of pull-up and pull-down impedance mismatch. Using a pull-up output value XZQ as a target level, each 0.5-bit difference is shown in + and − directions. Thus a pull-down output value DZQ#1 has an upper maximum 1-bit difference, and a pull-down output value DZQ#2 has a lower maximum 1-bit difference.
Consequently, when a mismatch between pull-up and pull-down resistances occurs, transmission error of output signals occurs or a median input signal is changed, potentially causing a setup/hold fail in a receiver.